Apple
CPU Gate Level Synthesis Engineer
$185K–$325K
Santa Clara, California · Full-time · Posted Apr 14, 2026
- Experience
- 10+ years of relevant industry experience.
- Education
- BS
About the job
Drive early-stage CPU design development by running RTL-to-gate synthesis and optimizing timing, power, and area.
What you'll do
- Assess RTL health and identify timing or gate-depth issues; collaborate on solutions.
- Estimate and validate power, improve synthesis flows, and track PPA trends.
- Integrate DFT requirements and partner with timing teams on constraints generation.
What they ask for
- BS degree.
- 10+ years of relevant industry experience.
- Experience in digital logic design, RTL synthesis, and physical design.
Nice to have
- CPU implementation experience.
- Proficiency in Tcl, Perl, or Python for automation and flow optimization.
Pay
USD $184,700 to $324,800 base salary
Tools
RTL, Tcl, Perl, Python, ATPG, MBIST
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