Apple
CPU Gate Level Synthesis Engineer
$150K–$278K
Santa Clara, California · Full-time · Posted Apr 14, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- BS
About the job
Develops and optimizes CPU RTL-to-gate-level synthesis to improve performance, power, and area, and provides early design-quality feedback.
What you'll do
- Assess RTL health and identify timing or gate-depth issues; collaborate on solutions.
- Estimate and validate power, debug PPA issues, and track PPA trends.
- Improve synthesis flows and constraints, and integrate DFT features with cross-functional teams.
What they ask for
- BS degree and 3+ years of relevant industry experience.
- Experience in digital logic design, RTL synthesis, and physical design.
Nice to have
- CPU implementation experience.
- Proficiency in TCL, Perl, or Python for automation and flow optimization.
Pay
$150,400 to $277,600 USD base salary
Tools
RTL, TCL, Perl, Python, ATPG, MBIST
Model-written summary · the original posting is authoritative