Drimva

Apple

CPU Microarchitect/RTL Engineer - Execution, Load/Store

$166K–$325K

Beaverton, Oregon +2 · Full-time · Posted Oct 27, 2025

Location
Beaverton, Oregon
Santa Clara, California
Waltham, Massachusetts
Experience
10+ years of relevant industry experience.
Education
Minimum BS.

About the job

Develop CPU microarchitecture and RTL for high-performance processor execution units, and support verification, performance assessment, and physical design delivery.

What you'll do

  • Develop microarchitecture and specifications, and own or refine RTL to meet power, performance, area, and timing goals.
  • Support functional verification through testbench development, formal methods, and simulation/emulation; assess performance against targets.
  • Collaborate with cross-functional teams on physical design implementation and verification, including timing, area, reliability, testability, and power.

What they ask for

  • Minimum BS degree.
  • Experience with microprocessor architecture and logic design principles, including timing and power implications.
  • Experience in Verilog or VHDL.
  • Experience with simulators and waveform debugging.

Nice to have

  • Expertise in one or more areas including out-of-order execution, instruction scheduling, execution units, load/store execution, or cache and memory subsystems; understanding of low-power and high-performance CPU microarchitecture techniques.
  • Experience in C or C++ and an interpretive language such as Perl or Python.

Pay

$184,700 and $324,800 USD base salary; $165,800 and $292,400 USD base salary

Tools

Verilog, VHDL, C, C++, Perl, Python

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 4, 2026 (UTC)