Drimva

Apple

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

$129K–$195K

Santa Clara, California · Full-time · Posted Jul 30, 2026

Education
Minimum BS

About the job

Drive architecture and RTL development for CPU front-end and/or out-of-order subsystems, from specification through verification and design delivery.

What you'll do

  • Develop microarchitecture and specifications through architectural exploration and research.
  • Own, assess, and refine RTL to meet power, performance, area, and timing goals; support functional verification.
  • Explore and verify performance, and collaborate with engineering teams on physical design implementation.

What they ask for

  • Minimum BS.

Nice to have

  • Microprocessor architecture and logic design experience, including timing and power implications.
  • Experience with Verilog or VHDL, simulators and waveform debugging, CPU execution or memory subsystems, low-power and high-performance microarchitecture, C or C++, or Perl or Python.

Pay

$129,300 and $194,700 (base salary)

Tools

Verilog, VHDL, C, C++, Perl, Python

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)