Apple
CPU Microarchitect/RTL Engineer - Fetch, Out of Order
$166K–$325K
Beaverton, Oregon +2 · Full-time · Posted Apr 14, 2026
- Location
- Beaverton, Oregon
Santa Clara, California
Waltham, Massachusetts - Experience
- 10+ years of relevant industry experience.
- Education
- Minimum BS
About the job
Leads or contributes to CPU front-end and out-of-order subsystem architecture and RTL development, verification, performance exploration, and design delivery.
What you'll do
- Develop microarchitecture and specifications from architectural exploration through detailed design.
- Own, assess, and refine RTL to meet power, performance, area, and timing goals; support verification and performance correlation.
- Work with engineering teams to implement and verify physical design for timing, area, reliability, testability, and power.
What they ask for
- Minimum BS degree and 10+ years of relevant industry experience.
- Experience with microprocessor architecture and logic design principles, including timing and power implications.
- Experience in Verilog or VHDL.
- Experience with simulators and waveform debugging.
Nice to have
- Expertise in instruction fetch and decode, branch prediction, instruction scheduling, register renaming, or out-of-order execution; understanding of low-power and high-performance CPU microarchitecture techniques.
- Experience in C or C++ and an interpretive language such as Perl or Python.
Pay
$184,700 and $324,800 USD base salary; $165,800 and $292,400 USD base salary
Tools
Verilog, VHDL, C, C++, Perl, Python
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