Drimva

Apple

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

$150K–$278K

Santa Clara, California · Full-time · Posted Oct 27, 2025

Experience
3+ years of relevant industry experience.
Education
Minimum BS.

About the job

Develop CPU front-end and/or out-of-order subsystem architecture and RTL for high-performance, low-power processor cores, supporting verification and design delivery.

What you'll do

  • Develop microarchitecture and specifications, from architectural exploration through detailed design.
  • Own and refine RTL to meet power, performance, area, and timing goals; support functional verification.
  • Explore and correlate performance, and work with cross-functional teams on physical design implementation and verification.

What they ask for

  • Experience with microprocessor architecture.
  • Experience with logic design principles and their timing and power implications.
  • Experience in Verilog or VHDL.
  • Experience with simulators and waveform debugging.

Nice to have

  • Expertise in out-of-order execution or related CPU execution, cache, and memory subsystems; understanding of low-power and high-performance microarchitecture techniques.
  • Experience with C or C++ and an interpretive language such as Perl or Python.

Pay

$150,400 and $277,600 USD base salary

Tools

Verilog, VHDL, C, C++, Perl, Python

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)