Apple
CPU Power Management Microarchitect/RTL Engineer
$166K–$325K
Beaverton, Oregon +2 · Full-time · Posted Apr 14, 2026
- Location
- Beaverton, Oregon
Santa Clara, California
Waltham, Massachusetts - Experience
- 10+ years of relevant industry experience.
- Education
- Minimum BS.
About the job
Architects and implements CPU power-management microarchitecture and RTL, supporting verification, performance exploration, and physical design delivery.
What you'll do
- Develop microarchitecture and detailed specifications for CPU power-management solutions.
- Own and refine RTL to meet power, performance, area, and timing goals; support functional verification.
- Explore and correlate performance, and collaborate on physical design implementation and verification.
What they ask for
- Experience with microprocessor architecture.
- Experience with logic design principles and their timing and power implications.
- Experience in Verilog or VHDL.
- Experience with simulators and waveform debugging.
Nice to have
- Expertise in areas such as DVFS/DVFM, thermal and energy management, power states, clocking, or power integrity.
- Experience in C or C++, Perl, or Python; understanding of low-power or high-performance CPU microarchitecture techniques.
Pay
$184,700 and $324,800 USD base salary; $165,800 and $292,400 USD base salary
Tools
Verilog, VHDL, C, C++, Perl, Python
Model-written summary · the original posting is authoritative