CPU Power Management Microarchitect/RTL Engineer

What you'll do

• Develop microarchitecture and specifications, from early architectural exploration through detailed design.
• Own or refine RTL to meet power, performance, area, and timing goals; support verification using test benches, formal methods, and simulation/emulation.
• Explore and correlate performance, and work with cross-functional teams on physical design considerations including timing, area, reliability, testability, and power.

What they ask for

• Minimum BS and 3+ years of relevant industry experience.
• Experience with microprocessor architecture and logic design principles with timing and power implications.
• Experience in Verilog or VHDL.
• Experience with simulators and waveform debugging.

Nice to have

• Expertise in one or more listed areas such as DVFS/DVFM, thermal and energy management, power states, dynamic clocking, or Di/dt mitigation.
• Understanding of low-power and high-performance CPU microarchitecture techniques; experience in C or C++, Perl, or Python.

Pay

$150,400 to $277,600 USD base salary

Tools

Verilog, VHDL, C, C++, Perl, Python