Apple
CPU Processor Power Management Verification Engineer
$150K–$278K
Santa Clara, California · Full-time · Posted Apr 14, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- Minimum BS; Master’s degree preferred.
About the job
Verifies CPU power management and clock control logic through simulation, emulation, FPGA, and formal verification, collaborating with design and silicon teams.
What you'll do
- Develop and execute test plans, tests, coverage monitors, checkers, and assertions for power management and clock control logic.
- Root-cause failures, recommend design solutions, and support silicon bringup and debug.
- Apply formal verification and verify designs in simulation, emulation, and FPGA environments.
What they ask for
- Minimum BS and 3+ years of relevant industry experience.
- Experience with digital logic, micro-processor architecture, or power management architecture.
- Experience with digital design verification, including Verilog/System-Verilog based testbenches and transactors checkers.
- Programming skills in scripting languages such as Perl or Python.
Nice to have
- Master’s degree preferred.
- Experience in processor or power management architecture and verification; random constraint verification, UVM base testbenches, assertions, silicon bringup, UPF, low power simulation, or formal verification.
Pay
$150,400 and $277,600 (base salary)
Tools
Assembly, Scripts, System Verilog, Verilog, Perl, Python, UVM, UPF
Model-written summary · the original posting is authoritative