Apple
CPU Processor Power Management Verification Engineer
$185K–$325K
Santa Clara, California · Full-time · Posted Apr 14, 2026
- Experience
- 10+ years of relevant industry experience.
- Education
- Minimum BS.
About the job
Verifies CPU power management and clock control logic through simulation, emulation, and silicon bringup, working with architecture, RTL, and silicon teams.
What you'll do
- Develop and execute test plans, tests, coverage monitors, checkers, and assertions for power management and clock control logic.
- Debug failures, identify root causes, and propose design solutions; support tests and debug in emulation, FPGA, and silicon bringup.
- Apply formal verification and analyze coverage to confirm test-plan coverage.
What they ask for
- Experience in digital logic, microprocessor architecture, or power management architecture.
- Experience with digital design verification, including Verilog/System-Verilog-based testbenches, transactors, and checkers.
- Experience with random constraint verification or UVM-based testbenches.
- Programming skills in Perl or Python.
Nice to have
- Master’s degree; in-depth knowledge of power management architecture and design techniques.
- Experience with SystemVerilog assertions, silicon bringup, UPF, low-power simulation, or formal verification.
Pay
$184,700 and $324,800 (USD, base salary)
Tools
Assembly, Scripts, System Verilog, Verilog, System-Verilog, Perl, Python, UPF
Model-written summary · the original posting is authoritative