Drimva

Apple

Data Center Hardware Engineering - Hardware System Integration Engineer

$150K–$278K

Sunnyvale, California · Full-time · Posted Jul 28, 2026

Experience
3+ years of relevant industry work experience in hardware or systems engineering; 7+ years is preferred.
Education
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent work experience.

About the job

Owns end-to-end hardware engineering for high-performance compute platforms, from specifications and schematic capture through bring-up, validation, and factory production support.

What you'll do

  • Design hardware systems and capture schematics; guide board layout and manage design constraints.
  • Run signal-integrity simulation, board bring-up, validation, and systematic hardware debugging.
  • Develop specifications and integration documentation, collaborate across engineering teams, and support factory builds and sustaining engineering.

What they ask for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent work experience.
  • Working knowledge of common low- and high-speed digital interfaces, including I2C/SMBus, SPI, JTAG, USB, PCIe, Ethernet, and DDR memory.
  • Broad circuit design experience across multiple domains and experience with PCB bring-up and characterization using standard EE lab equipment.
  • Ability to debug complex hardware issues from system level to circuit/transistor level; strong communication and technical documentation skills.

Nice to have

  • High-speed PCB design experience, including 10+ layer boards, material selection, and stackup definition; proficiency with Cadence tools or equivalent.
  • Hands-on high-speed serial protocol experience, familiarity with computer architecture, scripting experience, or a Master's degree in Electrical Engineering or Computer Engineering.

Pay

$150,400 to $277,600 USD base salary

Tools

PCIe, Ethernet, USB, DDR, I2C/SMBus, SPI, JTAG, Cadence

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 4, 2026 (UTC)