Apple
DDR Design Engineer
$185K–$325K
Cupertino, California · Full-time · Posted Nov 17, 2025
- Experience
- Minimum 10 years of relevant experience.
- Education
- BS degree in technical discipline.
About the job
Designs and verifies DDR PHY logic from concept and architecture through RTL development, silicon bring-up, and performance and power characterization.
What you'll do
- Conduct concept studies and guide design trade-offs for performance, gate count, and power; write design specifications and test plans with partner teams.
- Develop RTL with assertions, use formal tools and static checkers, and support verification, coverage, and timing closure.
- Support silicon bring-up and characterize performance and power.
What they ask for
- BS degree in a technical discipline.
- Minimum 10 years of relevant experience.
Nice to have
- RTL design using Verilog or SystemVerilog and assertion writing; experience designing state machines, data paths, arbitration, or clock domain crossing logic.
- Logic synthesis, timing constraints, DFT, Unified Power Format, equivalence checking, or prior DDR PHY design and mixed-signal experience.
Pay
$184,700 and $324,800 USD base salary
Tools
Verilog, SystemVerilog, Unified Power Format
Model-written summary · the original posting is authoritative