Apple
Design Verification Engineer
$150K–$278K
San Francisco Bay Area, California · Full-time · Posted Oct 26, 2026
- Experience
- Minimum 3 years of relevant industry experience, or equivalent.
- Education
- BS degree in a technical subject area; MS degree preferred.
About the job
Develops and executes pre-silicon verification for SoC/IP designs to help deliver functional first silicon.
What you'll do
- Create verification plans from design specifications and develop scalable verification environments, stimulus, checkers, assertions, and coverage.
- Run regressions, debug failures, close bugs, and track verification progress through coverage and other metrics.
- Use LLMs to improve verification efficiency and quality.
What they ask for
- BS degree in a technical subject area and at least 3 years of relevant industry experience or equivalent.
- Strong knowledge of OOP, SystemVerilog, and UVM.
- Strong knowledge of developing scalable and portable testbenches.
- Proven experience with verification methodologies and tools, including simulators, waveform viewers, automation, coverage collection, and gate-level simulations.
Nice to have
- MS degree in a technical subject area and relevant industry experience.
- Working experience with LLMs; experience with UPF, scripting languages, protocols, or formal verification is also noted.
Pay
$150,400 and $277,600 (base salary)
Tools
SystemVerilog, UVM, LLMs, UPF, Python, Perl, TCL, PCIe
AI focus
Use LLMs and related technologies to improve verification efficiency and quality.
Model-written summary · the original posting is authoritative