Apple
Design Verification Engineer
Beaverton, Oregon · Full-time · Posted Sep 10, 2026
- Experience
- Minimum 10 years of relevant industry experience.
- Education
- BS degree in technical subject area.
About the job
Develops and executes pre-silicon verification for SoC/IP designs to help deliver functional first silicon.
What you'll do
- Create test plans from design specifications and develop verification methodology and environments.
- Build SystemVerilog/UVM infrastructure, including stimulus, checkers, assertions, and coverage; run regressions and debug failures.
- Track verification progress and use LLMs to improve verification efficiency and quality.
What they ask for
- BS degree in a technical subject area.
- Minimum 10 years of relevant industry experience.
Nice to have
- Deep knowledge of OOP, SystemVerilog, and UVM; scalable, portable testbench development and verification tools/methodologies.
- Experience with LLMs, power-aware verification (UPF), scripting languages, protocols, formal verification, or emulation.
Tools
SystemVerilog, UVM, LLM, UPF, Python, Perl, TCL, PCIe
AI focus
Use LLMs and related technologies to improve verification efficiency and quality.
Model-written summary · the original posting is authoritative