Design Verification Engineer

What you'll do

• Develop test plans, coverage-driven plans, and reusable UVM testbenches for design components.
• Implement verification from RTL simulation bring-up through sign-off; debug failures and maintain regressions.
• Use LLMs and ML-driven workflows to improve verification efficiency and quality.

What they ask for

• Bachelor’s degree.
• Knowledge of System Verilog and UVM.
• Experience with System C, C/C++, Python/perl; ability to develop Python-based automation solutions.
• Ability to develop DV methodologies, use LLMs and MCPs, and understand constraint random testing, SVA, and coverage-driven verification.

Nice to have

• Master of Science degree in Electrical Engineering/Computer Science.
• Experience or knowledge in C/C++ modeling, 4G/5G cellular physical layer operation (3GPP), embedded processor cores, bus fabrics, or LLM workflow optimization.

Pay

$122,700 and $214,300 (USD, base salary); $129,300 and $225,300 (USD, base salary)

Tools

System Verilog, UVM, System C, C/C++, Python/perl, LLMs, MCPs, SVA

AI focus

Leverage LLMs and develop ML-driven workflows to improve verification efficiency and quality; preferred knowledge includes prompt engineering and LLM workflow optimization.