Apple
Design Verification Engineer
$166K–$292K
Cary, North Carolina +2 · Full-time · Posted Oct 27, 2026
- Location
- Cary, North Carolina
Melbourne, Florida
Waltham, Massachusetts - Experience
- Minimum 10 years relevant industry experience or equivalent.
- Education
- BS degree in technical subject area.
About the job
Verifies SoC and IP designs before silicon fabrication by building verification plans and environments, running regressions, debugging failures, and closing coverage and sign-off activities.
What you'll do
- Create test plans and develop SystemVerilog/UVM verification infrastructure to stress designs.
- Run and debug regressions, resolve failures, close bugs, and track verification progress and coverage.
- Use LLMs to improve verification efficiency and quality.
What they ask for
- BS degree in a technical subject area and a minimum 10 years of relevant industry experience or equivalent.
- Deep knowledge of OOP, SystemVerilog, and UVM.
- Deep knowledge of developing scalable and portable test-benches.
- Strong experience with verification methodologies and tools, including simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations.
Nice to have
- Working experience using LLMs for efficiency and quality.
- Experience with power-aware (UPF) or similar verification methodology; scripting language knowledge, protocol experience, formal verification, and emulation are also noted as preferences or pluses.
Pay
$165,800 and $292,400 (base salary range)
Tools
SystemVerilog, UVM, LLMs, UPF, Python, Perl, TCL, PCIe
AI focus
Use LLMs and related technologies to improve verification efficiency and quality.
Model-written summary · the original posting is authoritative