Design Verification Engineer

What you'll do

• Create verification plans and develop SystemVerilog/UVM environments, including stimulus, checkers, assertions, and coverage.
• Run regressions, debug failures, close bugs, and track verification progress through coverage and other metrics.
• Use LLMs to improve verification efficiency and quality.

What they ask for

• BS degree in a technical subject area and a minimum of 10 years of relevant industry experience or equivalent.
• Deep knowledge of OOP, SystemVerilog, and UVM.
• Strong experience with verification methodologies and tools, including simulators, waveform viewers, automation, coverage collection, or gate-level simulations.
• Excellent knowledge of one scripting language such as Python, Perl, or TCL.

Nice to have

• Working experience using LLMs for efficiency and quality; experience with power-aware (UPF) or similar verification methodology.
• Experience with PCIe, USB, or DDR; formal verification or emulation knowledge is a plus.

Tools

SystemVerilog, UVM, LLMs, UPF, Python, Perl, TCL, PCIe

AI focus

Use LLMs and related technologies to make verification more efficient and improve quality.