Apple
Design Verification Engineer
$175K–$325K
Austin, Texas +2 · Full-time · Posted Jun 11, 2026
- Location
- Austin, Texas
San Diego, California
Sunnyvale, California - Experience
- BS and a minimum of 10 years relevant industry experience.
- Education
- BS
About the job
Verifies cellular baseband modem and RF link-controller silicon through reusable UVM environments, coverage-driven testing, debug, and sign-off.
What you'll do
- Create component test plans, coverage-driven verification plans, and reusable UVM test benches.
- Implement verification from RTL simulation bring-up through sign-off; debug failures and maintain regressions.
- Use LLMs and ML-driven workflows to improve verification efficiency and quality.
What they ask for
- Strong knowledge of System Verilog and UVM; skilled in System C, C/C++, and Python/perl.
- Highly proficient in developing and establishing DV Methodologies.
- Experience with LLMs and MCPs, Python-based automation, constraint random testing, SVA, and Coverage driven verification.
- Strong test planning and problem-solving skills.
Nice to have
- Master of Science degree in Electrical Engineering/Computer Science; C/C++ modeling for design verification.
- Knowledge of 4G/5G cellular physical layer operation (3GPP), embedded processor cores, or bus-fabric verification.
Pay
$175,000 and $308,500 (base salary); $184,700 and $324,800 (base salary)
Tools
System Verilog, UVM, System C, C/C++, Python/perl, LLMs, MCPs, SVA
AI focus
Leverage LLMs and design ML-driven workflows to improve verification efficiency, productivity, and quality.
Model-written summary · the original posting is authoritative