Apple
Design Verification Engineer
$185K–$325K
San Francisco Bay Area, California · Full-time · Posted Oct 21, 2026
- Experience
- Minimum 10 years of relevant industry experience.
- Education
- BS degree in technical subject area.
About the job
Develop and execute pre-silicon verification for SoC/IP designs to help ensure functional first silicon.
What you'll do
- Create test plans and develop SystemVerilog/UVM verification infrastructure, including stimulus, checkers, assertions, and coverage.
- Run regressions, debug failures, fix bugs, and track verification progress through coverage and other metrics.
- Use LLMs to improve verification efficiency and quality.
What they ask for
- BS degree in a technical subject area.
- Minimum 10 years of relevant industry experience.
Nice to have
- Deep knowledge of OOP, SystemVerilog, and UVM; scalable and portable testbench development; verification methodologies and tools.
- Working experience using LLMs; power-aware verification; scripting languages such as Python, Perl, or TCL; protocol, formal verification, or emulation experience.
Pay
$184,700 and $324,800 (base salary)
Tools
SystemVerilog, UVM, LLMs, Python, Perl, TCL, UPF, PCIe
AI focus
Use LLMs and related technologies to improve verification efficiency and quality.
Model-written summary · the original posting is authoritative