Apple
Design Verification Engineer
Austin Metro Area, Texas · Full-time · Posted Oct 29, 2026
- Experience
- Minimum 3 years relevant industry experience or equivalent; relevant industry experience is preferred for the MS qualification.
- Education
- BS degree in a technical subject area; MS degree in a technical subject area preferred.
About the job
Performs pre-silicon design verification for SoC/IP designs, developing and executing plans and environments to support functional first silicon.
What you'll do
- Create test plans from design specifications and develop SystemVerilog/UVM verification infrastructure.
- Run verification and regressions, debug failures, close bugs, and track progress using coverage and other metrics.
- Use LLMs to improve verification efficiency and quality.
What they ask for
- BS degree in a technical subject area and a minimum 3 years relevant industry experience or equivalent.
- Strong knowledge of OOP, SystemVerilog and UVM.
- Strong knowledge of developing scalable and portable testbenches.
- Proven experience with verification methodologies and tools, including simulators, waveform viewer, automation, coverage collection, and gate-level simulations.
Nice to have
- MS degree in a technical subject area and relevant industry experience.
- Experience using LLMs, power-aware (UPF) verification, scripting languages, serial or parallel protocols, or formal verification.
Tools
SystemVerilog, UVM, LLMs, UPF, Python, Perl, TCL, PCIe
AI focus
Use LLMs and related technologies to improve verification efficiency and quality.
Model-written summary · the original posting is authoritative