Apple
Emulation Verification Engineer
Beaverton, Oregon · Full-time · Posted Jul 16, 2025
- Experience
- Minimum of 3 years of relevant industry experience.
- Education
- BS
About the job
Bring up large SoCs on emulation platforms and verify their functionality through test planning, stimulus, checkers, and low-power testing.
What you'll do
- Port designs to the Palladium platform and develop and execute emulation test plans.
- Create synthesizable monitors, checkers, stimulus, and verification code; develop random stimulus using existing UVM simulation constraints.
- Collaborate across architecture, design, verification, validation, power, and software teams; perform low-power testing and test-plan reviews.
What they ask for
- BS degree and 3 years of relevant industry experience.
- No other qualifications are stated as minimum requirements.
Nice to have
- Experience with emulator or FPGA flows, synthesizable Verilog/SystemVerilog, assertions, UVM, C/C++ DPI, test firmware, or scripting.
- Understanding of RTL-to-emulation tool flow; UVM Acceleration experience is a plus.
Tools
Palladium, Verilog, System Verilog, UVM, C/C++ DPI, Perl, Python, TCL
Model-written summary · the original posting is authoritative