Apple
Emulation Verification Engineer
Beaverton, Oregon · Full-time · Posted Apr 10, 2026
- Experience
- Minimum of 10 years of relevant industry experience.
- Education
- BS
About the job
Develop and support emulation environments for large SoCs, including design bring-up, verification test planning, and low-power testing.
What you'll do
- Port designs to the Palladium emulation platform and develop synthesizable monitors, checkers, and stimulus.
- Create and review emulation test plans; perform low-power testing and collaborate with cross-functional teams.
- Develop design and verification code and random-stimulus infrastructure using existing UVM simulation constraints.
Nice to have
- Understanding of RTL-to-emulation tool flow and experience with an emulator or FPGA flow.
- Verification experience with synthesizable Verilog/SystemVerilog, assertions, UVM, C/C++ DPI, firmware, or scripting.
Tools
Palladium, Verilog, System Verilog, UVM, C/C++ DPI, Perl, Python, TCL
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