Apple
FE RTL Infrastructure - CAD Engineer
$150K–$278K
Beaverton, Oregon +1 · Full-time · Posted Jun 11, 2026
- Location
- Beaverton, Oregon
Cupertino, California - Experience
- 3 years of relevant experience.
- Education
- BS degree
About the job
Develop and support RTL design and verification infrastructure, configuration management, and AI solutions that improve engineering productivity and reliability.
What you'll do
- Support RTL gatekeeping, design and verification collateral, and soft IP development and release methodologies; contribute to Perforce administration.
- Maintain a centralized configuration management system for loading design views into Front-End flows.
- Build generative AI solutions, identify productivity and reliability improvements, and maintain training materials and coordinate vendor training.
What they ask for
- Minimum BS degree and 3 years of relevant experience.
- Expertise programming in Python or Perl.
- Knowledge of Verilog and SystemVerilog.
Nice to have
- Experience with Front-End EDA tools such as Clock Domain Crossing, Reset Domain Crossing or Lint; understanding of Front-End RTL Build or Construction flows.
- Communication, debugging and root-cause skills; customer-oriented support experience; large-scale software development experience; MSEE/CE/CS.
Pay
USD $150,400 to USD $277,600 base salary
Tools
Python, Perl, Verilog, SystemVerilog, Perforce, Clock Domain Crossing, Reset Domain Crossing, Lint
AI focus
Build generative AI solutions across infrastructure systems and identify ways AI can accelerate engineering productivity and improve infrastructure reliability.
Model-written summary · the original posting is authoritative