Apple
FE RTL Infrastructure - CAD Engineer
$129K–$195K
Beaverton, Oregon +1 · Full-time · Posted Jun 11, 2026
- Location
- Beaverton, Oregon
Cupertino, California - Education
- Minimum BS degree; MSEE/CE/CS preferred.
About the job
Develop and support RTL design and verification infrastructure, including gatekeeping, configuration management, Perforce administration, and generative AI solutions that improve engineering productivity and reliability.
What you'll do
- Build and maintain infrastructure and flows used by RTL design and verification teams, including RTL gatekeeping and configuration management.
- Support Perforce administration and soft IP development and release methodologies.
- Develop generative AI solutions, identify AI opportunities, and maintain training materials and coordinate vendor training.
What they ask for
- Minimum BS degree.
- Expertise in programming in Python or Perl.
- Knowledge of Verilog and SystemVerilog.
Nice to have
- Experience with Front-End EDA tools such as Clock Domain Crossing, Reset Domain Crossing or Lint; understanding of Front-End RTL Build or Construction flows.
- Excellent communication, debugging and root-cause analysis skills; customer-oriented mindset and support experience; experience contributing to large-scale software systems from specification to deployment; MSEE/CE/CS preferred.
Pay
USD 129,300–USD 194,700 base salary
Tools
Python, Perl, Verilog, SystemVerilog, Perforce
AI focus
Build generative AI solutions across infrastructure systems and identify opportunities for AI to accelerate engineering productivity and improve infrastructure reliability.
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