Apple
Front-End CAD Methodology Engineer – Design/DV Interface
$216K–$394K
San Francisco Bay Area, California · Full-time · Posted Feb 28, 2026
- Experience
- 15+ years of relevant experience.
- Education
- Minimum BS degree; MSEE/CE/CS preferred.
About the job
Develops and leads scalable front-end CAD methodologies and automation for RTL design and verification, including GenAI-enabled tools that improve engineering productivity and silicon verification workflows.
What you'll do
- Design, architect, and promote reusable methodology solutions across RTL Design and DV teams.
- Create, monitor, and maintain high-quality flows for static verification, formal verification, simulation, and emulation.
- Work with design and CAD teams to define requirements and drive adoption of methodology solutions.
What they ask for
- BS degree and 15+ years of relevant experience.
- Experience with Front-End ASIC workflows.
- Experience working directly with design and verification engineers to define requirements and implement solutions.
- Experience with artificial intelligence and machine learning.
Nice to have
- Experience with Cadence or Synopsys’ static/formal/dynamic verification tools; Python, TCL or Perl; JSON or YAML; Verilog and SystemVerilog; familiarity with VHDL.
- Demonstrated experience driving large-scale software system development from specification to deployment.
Pay
$216,200 and $394,000 (base salary)
Tools
Cadence, Synopsys, Python, TCL, Perl, JSON, YAML, Verilog
AI focus
Uses artificial intelligence, machine learning, and GenAI-driven capabilities to build tools and optimize engineering workflows.
Model-written summary · the original posting is authoritative