Apple
Gate-level SigEM/SEB/FIT CAD Engineer
$185K–$325K
Austin Metro Area, Texas +1 · Full-time · Posted Apr 15, 2026
- Location
- Austin Metro Area, Texas
San Francisco Bay Area, California - Experience
- Minimum of BS + 10 years of relevant industry experience.
About the job
Develops and deploys EM/SEB/FIT/SHE and thermal analysis methodologies, verification flows, and sign-off solutions for gate-level and transistor-level designs.
What you'll do
- Architect and own EM/SEB/thermal methodologies and flows, from development and automation through sign-off.
- Develop and maintain rule decks and verification methods; lead tool-to-silicon correlation studies and continuous improvement.
- Coordinate with design, integration, EDA vendor, and foundry teams; mentor engineers on analysis techniques.
What they ask for
- Experience with EM/SEB/FIT/SHE/thermal methodologies and calculations.
- Experience with current-density calculations, heating effects, and electromigration failure mechanisms.
- Experience in EDA tools and CAD flow development.
- Minimum of BS + 10 years of relevant industry experience.
Nice to have
- Proficiency in Tcl, Python, and/or Perl; experience in EM analysis such as extraction, timing, simulation, modeling, physical design, or physical verification.
- Hands-on knowledge of EMIR tools such as Voltus, Voltus-Fi, RedHawk-SC, or Totem; advanced packaging familiarity and/or AI/ML-driven CAD workflow expertise.
Pay
$184,700 and $324,800 (USD, base salary)
Tools
Tcl, Python, Perl, Voltus, Voltus-Fi, RedHawk-SC, Totem
AI focus
Preferred expertise in AI/ML-driven innovation for CAD workflows.
Model-written summary · the original posting is authoritative