Apple
Gate-level SigEM/SEB/FIT CAD Engineer
$150K–$278K
Austin Metro Area, Texas +1 · Full-time · Posted Apr 15, 2026
- Location
- Austin Metro Area, Texas
San Francisco Bay Area, California - Experience
- Minimum 3 years of relevant industry experience.
- Education
- Minimum BS.
About the job
Develops and supports gate- and transistor-level EM, SEB, FIT, self-heating, and thermal analysis methodologies and sign-off flows for advanced designs.
What you'll do
- Develop and maintain EM/SEB/thermal methodologies, solutions, rule decks, and verification flows.
- Support analysis and sign-off, including signal and power-grid EM, FIT budget validation, and 3DIC/interposer thermal integrity.
- Collaborate across design and technology teams and with EDA vendors and foundries on requirements, tool qualification, and methodology improvements.
What they ask for
- Experience with EM/SEB/FIT/SHE/Thermal methodologies and calculations.
- Minimum BS + 3 years of relevant industry experience.
Nice to have
- Understanding of current density, heating effects, and electromigration failure mechanisms; experience in EM-related analysis.
- Experience with EDA tools and CAD flow development; proficiency in at least one of Tcl, Python, or Perl.
Pay
USD $150,400 and USD $277,600 (base salary range)
Tools
Tcl, Python, Perl, Voltus, Voltus-Fi, RedHawk-SC, Totem
AI focus
Interest in AI/ML-driven innovation for CAD workflows; the role does not specify particular AI/ML duties.
Model-written summary · the original posting is authoritative