Apple
Integration Engineer
$129K–$195K
Santa Clara, California · Full-time · Posted Jul 30, 2026
- Experience
- +0 years of experience.
- Education
- Bachelor's Degree
About the job
Integrate and validate ASIC IP and RTL at the SoC level, supporting design quality, timing closure, and verification.
What you'll do
- Integrate IP and RTL, assemble top-level SoC designs, and ensure interfaces and interconnects are correctly implemented.
- Run and debug lint, CDC/RDC, synthesis, and timing constraints; collaborate with physical design and STA teams on timing closure.
- Maintain automated integration build and regression systems, support verification bring-up and debug, and document designs.
What they ask for
- Bachelor's Degree.
- Solid understanding of digital logic design and RTL development (SystemVerilog, Verilog).
- Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence).
- Experience with bus protocols and interface standards; knowledge of ASIC tool flows and scripting for automation.
Nice to have
- Strong debugging and problem-solving skills.
- Excellent communication and cross-functional collaboration.
Pay
$129,300 and $194,700 (base salary)
Tools
SystemVerilog, Verilog, Synopsys, Cadence, AXI, AHB, APB, Python
Model-written summary · the original posting is authoritative