Apple
Integration Engineer
$150K–$278K
Santa Clara, California · Full-time · Posted Jul 30, 2026
- Experience
- +3 Years of Experience
- Education
- Bachelor's Degree
About the job
Integrate and validate IP blocks and RTL in top-level SoC designs, supporting build, timing, and verification workflows.
What you'll do
- Integrate IP and RTL, assemble top-level SoC designs, and ensure interfaces and connectivity are correct.
- Run and debug lint, CDC/RDC, synthesis, and timing-closure workflows; support verification bring-up and debug.
- Maintain automated build and regression systems, design constraints and documentation, and participate in design reviews.
What they ask for
- Bachelor's Degree
- 3+ years of experience
Nice to have
- Digital logic and RTL development experience with SystemVerilog or Verilog; familiarity with SoC design flows and Synopsys or Cadence.
- Experience with bus protocols or interface standards, ASIC tool flows, and scripting for automation.
Pay
$150,400 and $277,600 (base salary)
Tools
SystemVerilog, Verilog, Synopsys, Cadence, AXI, AHB, APB, Python
Model-written summary · the original posting is authoritative