Apple
Low Power Design Engineer
$123K–$225K
Irvine, California +2 · Full-time · Posted Oct 27, 2026
- Location
- Irvine, California
San Diego, California
Sunnyvale, California - Education
- Bachelor’s degree.
About the job
Designs power management logic for complex wireless communication SoCs, from feature definition and implementation through verification, power analysis, and post-silicon support.
What you'll do
- Define and implement SoC power management features and logic.
- Work with cross-functional teams to verify the logic and support power analysis and post-silicon correlation.
- Provide post-silicon bring-up and debug support.
What they ask for
- Bachelor’s degree.
- Proven track record in power, clock, or reset management logic design; experience in power management logic verification and debug.
- Proficiency in Verilog and scripting languages (Shell, Perl or Python).
- Knowledge of ASIC low power design techniques, CDC, RDC, STA, UPF, and common SoC components.
Nice to have
- SoC-level power management logic or top-level integration experience.
- System architecture knowledge or post-silicon functional debug and power correlation experience.
Pay
$122,700 and $214,300 USD base salary; $129,300 and $225,300 USD base salary
Tools
Verilog, Shell, Perl, Python, CDC, RDC, STA, UPF
Model-written summary · the original posting is authoritative