Apple
Low Power Design Engineer
$175K–$325K
Irvine, California +2 · Full-time · Posted Oct 27, 2026
- Location
- Irvine, California
San Diego, California
Sunnyvale, California - Experience
- Minimum 10 years of relevant industry experience.
- Education
- BS
About the job
Designs power-management logic for complex wireless communication SoCs, supporting verification, power analysis, and post-silicon bring-up and debug.
What you'll do
- Define SoC power-management features and implement the logic.
- Work with XF teams to verify power-management logic; support power analysis and post-silicon correlation.
- Provide post-silicon bring-up and debug support.
What they ask for
- Proven track record designing power, clock, or reset management logic; experience with power-management logic verification and debug.
- Proficiency in Verilog and scripting languages (Shell, Perl or Python).
- Understand ASIC low-power design techniques; knowledge of CDC, RDC, STA and UPF.
- Knowledge and experience with common SoC components, such as CPU, fabric, and peripherals; strong problem-solving and analytical skills.
Nice to have
- SoC-level power-management logic or SoC top-level integration experience.
- System architecture knowledge or post-silicon functional debug and power-correlation experience.
Pay
$175,000 and $308,500 (USD, base salary); $184,700 and $324,800 (USD, base salary)
Tools
Verilog, Shell, Perl, Python, CDC, RDC, STA, UPF
Model-written summary · the original posting is authoritative