Apple
Mixed Signal Verification Engineer
$129K–$225K
Austin, Texas +1 · Full-time · Posted Sep 29, 2026
- Location
- Austin, Texas
Sunnyvale, California - Experience
- MS and at least 3 years of industry experience is preferred.
- Education
- Bachelor’s degree.
About the job
Models and verifies analog/RF blocks within large SoCs using RNM and SystemVerilog, including self-checking models, assertions, and mixed-signal simulation environments.
What you'll do
- Develop RNM RF/analog models in SystemVerilog, including self-checking techniques and appropriate accuracy levels.
- Create assertions and digital verification passing criteria for analog/digital specifications.
- Set up AMS simulations with analog designers and debug complex chip digital-on-top testbenches.
What they ask for
- Bachelor’s degree.
- Strong fundamentals in analog/RF circuit theory and topologies.
- Experience with RNM coding in SystemVerilog.
Nice to have
- MS and at least 3 years of industry experience.
- Experience with Cadence mixed signal verification, analog schematics, modeling mixed-signal/RF blocks, or high-frequency PLLs.
Pay
$129,300 and $225,300 (base salary)
Tools
RNM, SystemVerilog, Cadence mixed signal verification environment, AMS
Model-written summary · the original posting is authoritative