Mixed-Signal Verification Engineer

What you'll do

• Review specifications, define verification plans, and develop top- and block-level testbenches and tests in a UVM framework.
• Build reusable monitors and checkers; debug failures, manage bugs, and analyze and close coverage.
• Automate verification flows and improve methodology, including by leveraging AI; collaborate with analog design.

What they ask for

• BS degree and a minimum of 10 years of relevant industry experience.
• Industry verification experience with RF/mixed-signal blocks and SoCs.
• Experience building mixed-signal testbenches, checkers, and tests using System Verilog.
• UVM methodology and HDL (System Verilog, Verilog) verification experience; strong problem-solving, testing, and debugging skills; understanding of common analog/RF blocks.

Nice to have

• Experience with UPF, Python or Matlab; Virtuoso Composer, ADE, and HED.
• Wireless experience; expertise creating and using real-numbered analog behavioral models in System Verilog; Master's or PhD with at least 5+ years of hands-on mixed-signal verification experience.

Pay

$175,000 and $308,500 USD base salary; $184,700 and $324,800 USD base salary

Tools

UVM, System Verilog, Verilog, UPF, Python, Matlab, Virtuoso Composer, ADE

AI focus

Improve mixed-signal verification methodology by leveraging AI.