Apple
PHY Design Verification Engineer
$123K–$225K
San Francisco Bay Area, California +1 · Full-time · Posted Jul 15, 2026
- Location
- San Francisco Bay Area, California
San Diego, California - Experience
- Preferred: 2+ years of verification experience of wireless/wired communication block/subsystem.
- Education
- Minimum: bachelor’s degree. Preferred: MSEE.
About the job
Verify pre-silicon RTL for wireless PHY subsystems and interfaces, developing reusable testbenches and using coverage-driven methods to ensure design quality.
What you'll do
- Review PHY microarchitecture and specifications; create and refine verification plans to meet coverage targets.
- Build reusable testbenches, develop and run directed and constrained-random tests, debug failures, and drive issue closure.
- Analyze coverage, support validation using Palladium and/or FPGA, and use machine learning and AI technologies to identify design and testbench issues.
What they ask for
- Minimum requirement of a bachelor’s degree.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Excellent knowledge and experience with ASIC verification flows, including testbench development, constrained-random testing, and code/functional coverage.
Nice to have
- MSEE with 2+ years of verification experience of wireless/wired communication block/subsystem.
- Experience with Matlab/C reference models and bit-accurate verification; wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee; scripting; AI technologies; or Palladium/FPGA validation.
Pay
$122,700 and $214,300 USD (base salary); $129,300 and $225,300 USD (base salary)
Tools
Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Matlab/C, Palladium, FPGA, Python
AI focus
Use machine learning and AI technologies to identify design and testbench issues and ensure DV quality.
Model-written summary · the original posting is authoritative