Apple
PHY Design Verification Engineer
$166K–$325K
San Francisco Bay Area, California +2 · Full-time · Posted Oct 23, 2025
- Location
- San Francisco Bay Area, California
San Diego, California
Waltham, Massachusetts - Experience
- Minimum 10 years of relevant industry experience.
- Education
- BS
About the job
Verifies wireless PHY RTL and SoC interfaces before silicon production, developing reusable test benches and improving design quality through coverage-driven testing and validation.
What you'll do
- Develop verification plans, reusable test benches, reference models, and directed and constrained-random tests; debug failures and drive issue closure.
- Create and analyze coverage models and improve coverage with additional test cases.
- Apply machine learning and AI to identify design and test-bench issues; support PHY validation using Palladium and/or FPGA.
What they ask for
- BS degree.
- At least 10 years of relevant industry experience.
Nice to have
- Wireless/wired communications verification; knowledge of Bluetooth, UWB, WLAN, or Zigbee.
- Advanced Verilog, SystemVerilog, UVM, and SystemVerilog Assertion; ASIC verification flows, constrained-random testing, and coverage.
Pay
$175,000 and $308,500 USD (base salary); $165,800 and $292,400 USD (base salary); $184,700 and $324,800 USD (base salary)
Tools
Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Matlab/C, Palladium, FPGA, Python
AI focus
Use machine learning and AI technologies to identify design and test-bench issues; experience using AI for data mining/analysis is preferred.
Model-written summary · the original posting is authoritative