Apple
PHY Design Verification Engineer
$166K–$325K
San Francisco Bay Area, California +2 · Full-time · Posted Oct 21, 2026
- Location
- San Francisco Bay Area, California
San Diego, California
Waltham, Massachusetts - Experience
- Minimum 10 years relevant industry experience.
- Education
- BS
About the job
Verify wireless PHY RTL and subsystem interfaces before silicon production, building reusable verification environments and driving coverage and issue closure.
What you'll do
- Develop verification plans, reusable test benches, reference models, and directed or constrained-random tests; debug failures and track issues through resolution.
- Create and analyze coverage models, adding tests to meet coverage targets and improve verification quality.
- Apply AI and machine learning to identify design and test-bench issues, and support PHY validation using Palladium and/or FPGA.
What they ask for
- BS degree and at least 10 years of relevant industry experience.
- Verification experience with wireless or wired communication blocks/subsystems.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Experience with ASIC verification flows, including test-bench development, constrained-random testing, and code/functional coverage.
Nice to have
- Matlab/C reference models and bit-accurate verification; wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
- Shell, Python, or Perl scripting; AI technologies for data mining/analysis; Palladium/FPGA validation.
Pay
$175,000 and $308,500 USD (base salary); $165,800 and $292,400 USD (base salary); $184,700 and $324,800 USD (base salary)
Tools
Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Matlab/C, Palladium, FPGA, Python
AI focus
Use machine learning and AI technologies to identify design and test-bench issues; preferred experience includes AI for data mining/analysis.
Model-written summary · the original posting is authoritative