Apple
PHY Design Verification Engineer
$123K–$225K
San Francisco Bay Area, California +1 · Full-time · Posted Oct 21, 2026
- Location
- San Francisco Bay Area, California
San Diego, California - Education
- Bachelor’s degree required; MSEE preferred.
About the job
Performs pre-silicon RTL verification of wireless PHY designs and interfaces, developing reusable testbenches, tests, and coverage models to ensure design quality.
What you'll do
- Review PHY microarchitecture and specifications; create verification plans and coverage targets.
- Build reusable testbenches and reference models; develop and run directed and constrained-random tests, debug failures, and help close issues.
- Analyze coverage, support validation using Palladium and/or FPGA, and apply machine learning and AI to identify design and testbench issues.
What they ask for
- Bachelor’s degree.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Excellent knowledge and experience with ASIC verification flows, including testbench development, constrained-random testing, and code/functional coverage.
Nice to have
- MSEE with 2+ years of verification experience in wireless/wired communication blocks or subsystems; Matlab/C reference models and bit-accurate verification.
- Wireless protocol knowledge (Bluetooth, UWB, WLAN, or Zigbee); scripting in shell, Python, or Perl; AI data mining/analysis; Palladium/FPGA validation.
Pay
USD $122,700 to $214,300 base salary; USD $129,300 to $225,300 base salary
Tools
Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Matlab/C, Palladium, FPGA, Python
AI focus
Use machine learning and AI technologies to identify design and testbench issues; AI technologies for data mining/analysis are preferred.
Model-written summary · the original posting is authoritative