PLL Design Engineer

What you'll do

• Develop frequency synthesizers for multiple technology applications.
• Design and model PLL/FLL architectures and circuits.
• Perform behavioral simulations to evaluate architecture performance and loop dynamics.

What they ask for

• BSEE.
• At least 10 years of relevant experience.

Nice to have

• Proficiency in PLL/FLL and frequency-synthesis architecture and circuit design, including DCO/VCO, Fractional-N, SSC, spur, and jitter techniques.
• Experience with System Verilog models and behavioral simulation; RTL design/debug is a plus.

Pay

$184,700 and $324,800 (base salary)

Tools

PLL/FLL, DCO/VCO, Fractional-N, SSC, System Verilog, RTL