Apple
PLL Design Engineer
$175K–$308K
San Diego, California · Full-time · Posted Feb 26, 2026
- Experience
- At least 10 years of relevant experience.
- Education
- BSEE
About the job
Develop frequency synthesizers for Compute, SoC, SerDes, and Cellular applications as part of Apple’s Analog-Mixed/Signal group.
What you'll do
- Develop frequency synthesizers for a range of applications.
- Design PLL/FLL and frequency-synthesis architectures and circuits.
- Model and simulate architectures to assess performance and loop dynamics.
What they ask for
- BSEE.
- At least 10 years of relevant experience.
Nice to have
- Proficiency in PLL/FLL and frequency-synthesis architecture and circuit design, including DCO/VCO, Fractional-N, SSC, spur, and jitter techniques.
- Knowledge of clocking, phase noise, jitter analysis, System Verilog modeling, behavioral simulation, and scripting; RTL design/debug and industry-standard tools are a plus.
Pay
$175,000 and $308,500 (base salary)
Tools
PLL/FLL, DCO/VCO, Fractional-N, SSC, System Verilog, RTL
Model-written summary · the original posting is authoritative