Apple
RFIC Layout Engineer
Irvine, California +2 · Full-time · Posted Oct 8, 2025
- Location
- Irvine, California
San Diego, California
Sunnyvale, California - Experience
- 8+ year minimum related experience required
About the job
Designs and verifies transistor-level RF and analog layouts for wireless silicon, collaborating on floorplanning, integration, and layout quality checks.
What you'll do
- Create block-level and top-level RF/analog layouts and complete verification, including extraction, DRC, LVS, and DFM checks.
- Collaborate with circuit designers on floorplanning and resolve layout risks; review routing, electromigration, signal paths, matching, and coupling.
- Integrate and verify top-level layouts and manage schedules.
What they ask for
- 8+ year minimum related experience required.
- Good understanding of RC delay, electromigration, and coupling.
- Ability to identify failure-prone circuit and layout structures and work with circuit designers to resolve issues.
- Excellent communication skills and ability to work with multi-functional teams.
Nice to have
- Knowledge of layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing; experience with custom RF/analog layout, deep sub-micron CMOS (16nm and lower with FinFet experience).
- Knowledge of CALIBRE verification, CADENCE layout tools, process effects, and scripting in PERL or SKILL; ability to lead top-level integration.
Pay
$43.07 and $76.64/hr (base salary); $45.46 and $80.76/hr (base salary)
Tools
CALIBRE, CADENCE, PERL, SKILL, FinFet Technology
Model-written summary · the original posting is authoritative