Apple
RFIC Layout Engineer
$158K–$312K
San Francisco Bay Area, California +4 · Full-time · Posted Oct 27, 2026
- Location
- San Francisco Bay Area, California
Austin, Texas
Irvine, California
San Diego, California
Waltham, Massachusetts - Experience
- 10+ years of relevant industry experience.
- Education
- BS
About the job
Designs and verifies transistor-level RF and analog IC layouts for next-generation wireless radios in advanced CMOS processes, supporting production.
What you'll do
- Create transistor-level layouts for RF and analog circuit blocks and complete verification, including extraction, DRC, LVS, and DFM checks.
- Collaborate with designers on block floorplanning and review power/ground routing, electromigration, signal paths, matching, and coupling.
- Bring wireless technologies into high-volume production in advanced CMOS technology nodes.
What they ask for
- BS degree and 10+ years of relevant industry experience.
- FinFet experience.
Nice to have
- Custom RF/analog radio-transceiver layout experience and knowledge of deep sub-micron CMOS, matching, parasitic reduction, RF shielding, and high-frequency routing.
- Knowledge of CALIBRE DRC/ERC/LVS, CADENCE layout tools, and scripting in PERL or SKILL; understanding of RC delay, electromigration, coupling, guard rings, DNW, PN junctions, LOD, and WPE.
Pay
$166,600 and $296,000 USD base salary; $157,700 and $280,600 USD base salary; $175,500 and $311,700 USD base salary
Tools
CMOS, FinFet, CALIBRE, CADENCE, PERL, SKILL
Model-written summary · the original posting is authoritative