RTL Design Engineer

What you'll do

• Specify or micro-architect digital blocks and code RTL.
• Support design verification by writing assertions, debugging code, and working with the verification team.
• Contribute to lab bring-up by writing test scripts, analyzing lab data, and proposing experiments.

What they ask for

• Bachelor of Science in Electrical Engineering.

Nice to have

• Knowledge of RTL design and Verilog/SystemVerilog.
• Experience with mixed-signal concepts and analog circuit behavioral modeling.

Tools

Verilog, SystemVerilog, Perl, JSON, Python

AI focus

Use GenAI tools, including large language models and AI-assisted code generation, to design, validate, and optimize SystemVerilog RTL code.