Apple
RTL Design Engineer
Melbourne, Florida · Full-time · Posted Oct 21, 2025
- Experience
- Minimum of 10 years of relevant industry experience.
- Education
- BS
About the job
Design, verify, and support lab bring-up of digital and mixed-signal circuits, including specifying blocks and writing RTL.
What you'll do
- Specify or micro-architect digital blocks and code RTL.
- Support design verification through assertions, debugging, and collaboration with the verification team.
- Contribute to lab bring-up by writing test scripts, analyzing data, and proposing experiments.
What they ask for
- BS degree.
- Proven knowledge of RTL design, Verilog, and SystemVerilog.
- Deep knowledge of front-end tools, including simulators, linters, CDC, RDC, LEQ, and UPF.
- Knowledge of low-power design, ECO flows, mixed-signal concepts, synthesis, static timing, DFT, verification techniques, scripting, or related listed areas.
Nice to have
- Experience using GenAI tools to design, validate, and optimize SystemVerilog RTL code.
- Digital signal processing fundamentals and strong communication and presentation skills.
Tools
Verilog, SystemVerilog, Perl, JSON, Python, UPF
AI focus
Use GenAI tools, such as large language models and AI-assisted code generation, to design, validate, and optimize SystemVerilog RTL code.
Model-written summary · the original posting is authoritative