Drimva

Apple

RTL Design Engineer

Melbourne, Florida · Full-time · Posted Apr 10, 2026

Education
Bachelor of Science in Electrical Engineering.

About the job

Specify, design, verify, and support lab bring-up of digital and mixed-signal circuits, including RTL development and integration of mixed-signal and analog IP.

What you'll do

  • Specify or micro-architect digital blocks and write RTL code.
  • Support verification through assertions, debugging, and collaboration with the design verification team.
  • Contribute to lab bring-up by writing test scripts, analyzing data, and proposing experiments.

What they ask for

  • Bachelor of Science in Electrical Engineering.

Nice to have

  • Knowledge of RTL design, Verilog, and SystemVerilog.
  • Experience with mixed-signal concepts, analog behavioral modeling, verification, and related silicon design methods and tools.

Tools

Verilog, SystemVerilog, Perl, JSON, Python, GenAI tools, large language models

AI focus

Use GenAI tools, including large language models and AI-assisted code generation, to design, validate, and optimize SystemVerilog RTL code.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)