Apple
RTL Design Engineer
$175K–$308K
San Diego, California · Full-time · Posted Oct 21, 2025
- Experience
- Minimum of 10 years relevant industry experience.
- Education
- BS
About the job
Design, implement, verify, integrate, and support lab bring-up of digital and mixed-signal RTL blocks and signal-processing circuits.
What you'll do
- Specify or micro-architect digital and signal-processing blocks, and implement them in RTL, including DSP algorithms.
- Write assertions and testbenches, debug designs, and participate in functional verification.
- Integrate IP and support silicon lab characterization by writing test scripts, analyzing data, and validating signal-processing performance.
What they ask for
- BS degree.
- Minimum of 10 years of relevant industry experience.
Nice to have
- Front-end tools, synthesis, static timing analysis, DFT, formal verification, low-power design, and advanced verification techniques.
- DSP experience and intermediate-to-advanced GenAI proficiency for SystemVerilog design, validation, and optimization.
Pay
$175,000 to $308,500 USD base salary
Tools
Verilog, SystemVerilog, Perl, Python
AI focus
Use AI tools for SystemVerilog design, validation, and optimization, and understand GenAI capabilities and limitations in hardware design.
Model-written summary · the original posting is authoritative