Apple
RTL Design Engineer
$175K–$308K
Irvine, California · Full-time · Posted Dec 22, 2025
- Experience
- Minimum of 10 years of relevant industry experience.
- Education
- BS
About the job
Design, verify, integrate, and support lab bring-up of digital and mixed-signal RTL blocks, including signal-processing implementations.
What you'll do
- Specify or micro-architect digital and signal-processing blocks, then implement them in RTL.
- Translate DSP concepts into efficient RTL and contribute assertions, testbenches, and functional verification.
- Integrate IP and support silicon lab characterization, including test scripting, data analysis, and performance validation.
What they ask for
- BS degree.
- At least 10 years of relevant industry experience.
Nice to have
- Front-end tools, synthesis, static timing analysis, DFT, formal verification, low-power design, or advanced verification expertise.
- DSP implementation experience, scripting with Perl or Python, hardware-software co-design, or intermediate to advanced GenAI proficiency for SystemVerilog work.
Pay
$175,000 and $308,500 (base salary)
Tools
Verilog, SystemVerilog, Perl, Python
AI focus
Use AI tools for SystemVerilog design, validation, and optimization, and understand GenAI capabilities and limitations in hardware design.
Model-written summary · the original posting is authoritative