Apple
RTL Design Engineer
Austin, Texas · Full-time · Posted Oct 21, 2025
- Experience
- Minimum of 10 years relevant industry experience.
- Education
- BS
About the job
Design, verify, integrate, and support lab bring-up of RTL for mixed-signal digital circuits and signal-processing blocks.
What you'll do
- Specify or micro-architect digital and DSP blocks, and implement them in Verilog/SystemVerilog.
- Write assertions and testbenches; collaborate with verification teams to debug and validate designs.
- Integrate IP and support silicon lab characterization, including test scripting and signal-performance analysis.
What they ask for
- BS degree.
- Minimum of 10 years of relevant industry experience.
Nice to have
- Experience with front-end design tools, synthesis, static timing analysis, DFT, formal verification, low-power design, or advanced verification.
- DSP implementation experience, scripting with Perl or Python, hardware-software co-design, or intermediate-to-advanced GenAI proficiency for hardware design.
Tools
Verilog, SystemVerilog, Perl, Python
AI focus
Use GenAI tools for SystemVerilog design, validation, and optimization, and understand their capabilities and limitations in hardware design.
Model-written summary · the original posting is authoritative