Drimva

Apple

Sensing & Imaging FPGA Engineer

$175K–$325K

San Francisco Bay Area, California +1 · Full-time · Posted Aug 13, 2026

Location
San Francisco Bay Area, California
San Diego, California
Experience
Minimum 10 years of relevant industry experience.
Education
BS.

About the job

Develops FPGA platforms for camera and multi-sensor acquisition and processing, from architecture and RTL design through verification, hardware bring-up, and validation.

What you'll do

  • Define requirements and performance goals with cross-functional teams; contribute to system architecture and technology roadmaps.
  • Own RTL and FPGA implementation, including IP integration, synthesis, place and route, timing closure, and verification.
  • Build sensor-data processing systems and bring up, debug, validate, and document designs.

What they ask for

  • Proficiency with FPGA design tools such as Vivado or Lattice Radiant, and familiarity with AMD (Xilinx) and Lattice FPGA technologies.
  • Strong System Verilog or Verilog RTL design skills.
  • Experience with communication interfaces and protocols, including I2C, SPI, UART, USB, MIPI, DP, or high-speed serial interfaces.
  • Troubleshooting and analytical skills using lab equipment such as oscilloscopes, logic analyzers, ChipScope, and Reveal.

Nice to have

  • Experience implementing image or signal processing in FPGA; low-level software or Python/Tcl automation; CDC and FPGA timing constraints; CI/CD, version control, or regression testing.
  • AI-assisted coding and design experience; MS or PhD in a related field with FPGA design experience delivering FPGAs from concept to implementation.

Pay

$175,000 and $308,500 (base salary); $184,700 and $324,800 (base salary)

Tools

Vivado, Lattice Radiant, AMD (Xilinx), Lattice, System Verilog, Verilog, I2C, SPI

AI focus

Develops hardware systems supporting Apple Intelligence capabilities; AI-assisted coding and design experience is preferred.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)