Apple
Silicon Validation Engineer
$123K–$225K
Los Angeles Metro Area, California +1 · Full-time · Posted May 7, 2026
- Location
- Los Angeles Metro Area, California
San Francisco Bay Area, California - Education
- Bachelor’s degree required; MSEE preferred.
About the job
Leads laboratory bring-up, validation, characterization, and performance-margin testing of high-speed SerDes blocks for mobile SoCs.
What you'll do
- Bring up, validate, characterize, and debug SerDes blocks and components; assess signal integrity and adaptation.
- Develop and execute test methodologies to measure operating margins across PVT variations using high-speed lab equipment.
- Collaborate with ATE and Product Engineering teams on characterization, validation, and product release.
What they ask for
- Bachelor’s degree.
- Hands-on expertise with high-speed SerDes architectures, including NRZ and PAM, and associated protocols.
- Knowledge of SerDes blocks such as CTLE, DFE, FFE, CDR, and PLLs, including characterization and debugging.
- Experience with high-speed measurement equipment, signal integrity analysis, and protocols such as USB, PCIe, and DisplayPort.
Nice to have
- MSEE and relevant experience.
- Hands-on SerDes lab experience and Python programming experience.
Pay
$122,700 and $214,300 (base salary); $129,300 and $225,300 (base salary)
Tools
SerDes, NRZ, PAM, CTLE, DFE, FFE, CDR, PLLs
Model-written summary · the original posting is authoritative