Apple
SIPI Architect for High-Speed SerDes
$262K–$394K
San Francisco Bay Area, California +1 · Full-time · Posted Dec 3, 2025
- Location
- San Francisco Bay Area, California
Austin, Texas - Experience
- 20+ years of relevant industry experience.
- Education
- BS; preferred: MS or PhD in Electrical Engineering or a related field.
About the job
Defines and leads end-to-end signal and power integrity architecture for high-speed SerDes interconnects, ensuring robust performance from silicon through system.
What you'll do
- Set SIPI strategy and technical direction across circuit design, packaging, system hardware, and validation teams.
- Lead system-level trade-off analyses and oversee modeling, simulation, and silicon correlation.
- Guide technology roadmaps and develop next-generation SIPI methodologies and best practices.
What they ask for
- BS degree.
- 20+ years of relevant industry experience.
Nice to have
- MS or PhD in Electrical Engineering or a related field.
- Expertise in system-level SIPI for 112G/224G+ SerDes and experience with high-performance interconnect standards such as Ethernet, PCIe, UAL, and CXL.
Pay
$262,500 and $394,000 USD base salary
Tools
SerDes, Ethernet, PCIe, UAL, CXL, COM, co-packaged optics (CPO), PDN
Model-written summary · the original posting is authoritative